An analog-to-digital converter ADC means an apparatus for receiving an analog signal showed with successive values and converting the analog signal into a digital signal (n bits) showed with discrete positive value. The ADC includes a pipelined ADC, a successive approximation register SAR and an algorithmic ADC, etc.
FIG. 1 and FIG. 2 are views illustrating concept of a successive approximation register using conventional dual capacitor array.
Referring to FIG. 1, the conventional successive approximation register 100 using a dual capacitor array includes a dual capacitor array 110, a comparator 120 and an SAR logic circuit 130. Here, the successive approximation register 100 performs a sampling operation and a hold operation for converting a digital signal.
The capacitor 110 includes a first capacitor 110-1 for converting most significant bits MSBs of n bits and a second capacitor array 110-2 for converting lease significant bits LSBs of the n bits.
Particularly, one terminal of the second capacitor array 110-2 is connected to a ground in the event that the conventional successive approximation register 100 performs the sampling operation as shown in (a) in FIG. 1, and a reference voltage is applied to one terminal of the second capacitor array 110-2 in the event that the conventional successive approximation register 100 performs the hold operation as shown in (b) in FIG. 1.
That is, the dual capacitor array of the conventional successive approximation register 100 with single-ended structure separates the first capacitor array 110-1 for the MSB and the second capacitor array 110-2 for the LSB, thereby reducing switching energy.
However, the problem exists in that 90% or more of total switching energy is consumed (E=256C0VREF2) during the sampling process and the hold process in the conventional successive approximation register 100 with the dual capacitor array, as shown in FIG. 2.